The included silicone disconnect cap offers great value, disappearing small parasites

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The ubiquitous power rail decoupling capacitor, placed as close as possible to its load, plays a thankless role and often receives little respect compared to the features of high-end analog and digital devices. This is partly because these passive components do not “add value” to the track in the conventional functional sense.

Instead, their role is to maintain track quality despite load current transients and noise. In many designs, these capacitors are manufactured as discrete devices in the form of multilayer ceramic capacitors (MLCCs).

However, there is another physical realization of capacitors that offers performance benefits, utilizing silicon and its manufacturing processes. Empower Semiconductor was recently introduced the largest silicon capacitor in its ECAP product family for high-frequency decoupling.

Empower Semiconductor’s capacitor focuses on energy integrity

The EC1005P is a single capacitance 16.6 μF device suitable for the most demanding power integrity objectives commonly found in high-performance systems-on-chip (SoCs). It is offered in a compact chip-scale package (CSP) of 3,643 x 3,036 mm with 120 pads (Figure 1). The device comes in a standard 784 µm profile that can be adapted to different height requirements.

This low profile device has ultra-low impedance down to 1 GHz and can be embedded into the substrate or interposer of any SoC (Fig. 2). Thus, it is well suited for high-performance computing (HPC) and artificial intelligence (AI) applications.

When it comes to decoupling capacitors, the component and connection parasitics can quickly degrade their system-level performance. The EC1005P has an ultra-low equivalent series inductance (ESL) of less than 1 picohenries (pH, not the chemistry “pH”) and an equivalent series resistance (ESR) of less than 3 mΩ.

Filling the decoupling gap

Empower claims that the silicon capacitor technology fills the ‘last inch’ decoupling gap between the voltage regulators and the SoC power pins. This approach replaces several separate components with much lower performance and larger footprints with a single monolithic device that delivers optimal electrical performance and simplifies technical complexity.

In addition, these silicon capacitors provide high stability under overvoltage and overtemperature conditions and are not subject to derating or aging like traditional MLCCs. She require no AC or DC bias reduction, while all other reduction requirements are negligible. This eliminates the need to “over-specify” capacity requirements to account for derating.

If you’re unfamiliar with silicon capacitors, here’s a brief overview of the technology, along with its key features and a comparison to MLCCs. The EC1005P ECAP is now available for sampling and will enter series production in the fourth quarter of 2024.

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